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CS3011 CS3012 Precision Low-voltage Amplifier; DC to 1 kHz
Features & Description
Offset: 10 V Max Low Drift: 0.05 V/C Max Low Noise
Low
Description
The CS3011 single amplifier and the CS3012 dual amplifier are designed for precision amplification of lowlevel signals and are ideally suited to applications that require very high closed-loop gains. These amplifiers achieve excellent offset stability, super-high open-loop gain, and low noise over time and temperature. The devices also exhibit excellent CMRR and PSRR. The common mode input range includes the negative supply rail. The amplifiers operate with any total supply voltage from 2.7 V to 6.7 V (1.35 V to 3.35 V).
- 12 nV/Hz @ 0.5 Hz - 0.1 to 10 Hz = 250 nVp-p - 1/f corner @ 0.08 Hz
Open-loop
Voltage Gain
- 300 dB Typ - 200 dB Min
Rail-to-rail
Output Swing Slew Rate: 2 V/s
Pin Configurations
CS3011
PDWN 1 -In +In V2 3 4 + 8 7 6 5 NC V+ Output NC Out A 1 -In A 2 +In A 3 V- 4 A -+ +B
CS3012
8 V+ 7 Out B 6 -In B 5 +In B
Applications
Thermocouple/Thermopile
Amplifiers Load Cell and Bridge Transducer Amplifiers Precision Instrumentation Battery-powered Systems
8-lead SOIC
8-lead SOIC
Noise vs. Frequency (Measured)
100
nV/Hz
CS3011 Dexter Research Thermopile ST60
10
R2 64.9k
1 0.001
0.010
0.1 Frequency (Hz)
1
10
R1 100 C1 0.015F
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2009 (All Rights Reserved)
JUL `09 DS597F6
CS3011 CS3012
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS .................................................... 3 2. TYPICAL PERFORMANCE PLOTS ..................................................................... 4 3. CS3011/CS3012 OVERVIEW ............................................................................... 8
3.1 Open Loop Gain and Phase Response ......................................................................9 3.2 Open Loop Gain and Stability Compensation ...........................................................10 3.2.1 Discussion ................................................................................................10 3.2.2 Gain Calculations Summary and Recommendations .. .............................13 3.3 Powerdown (PDWN) .................................................................................................13 3.4 Applications ..............................................................................................................14
4. 5. 6. 7.
ORDERING INFORMATION .............................................................................. 15 ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ........ 15 PACKAGE DRAWING ........................................................................................ 16 REVISION HISTORY ......................................................................................... 17
LIST OF FIGURES
Figure 1. Noise vs. Frequency (Measured) ................................................................ 4 Figure 2. 0.01 Hz to 10 Hz Noise ............................................................................... 4 Figure 3. Supply Current vs. Temperature, 3011 ....................................................... 4 Figure 4. Noise vs. Frequency ................................................................................... 4 Figure 5. Offset Voltage Stability (DC to 3.2 Hz) ........................................................ 4 Figure 6. Supply Current vs. Temperature, 3012 ....................................................... 4 Figure 7. Supply Current vs. Voltage, 3011 ............................................................... 5 Figure 8. Supply Current vs. Voltage, 3012 ............................................................... 5 Figure 9. Open Loop Gain and Phase vs Frequency ................................................. 5 Figure 10. Open Loop Gain and Phase vs Frequency (Expanded) ........................... 6 Figure 11. Input Bias Current vs Common Mode Voltage (CS3012) ......................... 6 Figure 12. Voltage Swing vs. Output Current (2.7 V) ................................................. 7 Figure 13. Voltage Swing vs. Output Current (5 V) .................................................... 7 Figure 14. CS3011/CS3012 Open Loop Gain and Phase Response ........................ 9 Figure 15. Non-Inverting Gain Configuration ........................................................... 10 Figure 16. Non-Inverting Gain Configuration with Compensation ............................ 11 Figure 17. Loop Gain Plot: Unity Gain and with Pole-Zero Compensation .............. 12 Figure 18. Thermopile Amplifier with a Gain of 650 V/V .......................................... 14 Figure 19. Load Cell Bridge Amplifier and A/D Converter ........................................ 14 Figure 20.
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1. CHARACTERISTICS AND SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V+ = +5 V, V- = 0V, VCM = 2.5 V (Note 1) CS3011/CS3012 Parameter Input Offset Voltage Average Input Offset Drift Long Term Input Offset Voltage Stability Input Bias Current Input Offset Current Input Noise Voltage Density RS = 100 , f0 = 1 Hz RS = 100 , f0 = 1 kHz Input Noise Voltage Input Noise Current 0.1 to 10 Hz 0.1 to 10 Hz * (Note 4) (Note 5) * * * * Input Noise Current Density f0 = 1 Hz Input Common Mode Voltage Range Common Mode Rejection Ratio (dc) Power Supply Rejection Ratio Large Signal Voltage Gain RL = 2 k to V+/2 Output Voltage Swing RL = 2 k to V+/2 RL = 100 k to V+/2 Slew Rate Overload Recovery Time Supply Current PWDN active (CS3011 Only) PWDN Threshold Start-up Time CS3011 CS3012 (Note 6) (Note 6) (Note 7) * * * * * RL = 2 k, 100 pF TA = 25 C TA = 25 C * * -0.1 115 120 200 +4.7 (Note 2) (Note 2) * * Min Typ 0.01 (Note 3) 50 100 12 12 250 100 1.9 120 136 300 +4.99 2 600 0.9 1.7 (V+)-1.25 1.4 2.4 15 12 1000 2000 pA pA
nV/ Hz nV/ Hz
Max 10 0.05
Unit V V/C
nVp-p
fA/ Hz
pAp-p V dB dB dB V V V/s s mA mA A ms
(V+) -1.0 9
Notes: 1. Symbol "*" denotes specification applies over -40 to +85 C. 2. This parameter is guaranteed by design and laboratory characterization. Thermocouple effects prohibit accurate measurement of these parameters in automatic test systems. 3. 1000-hour life test data @ 125 C indicates randomly distributed variation approximately equal to measurement repeatability of 1 V. 4. Measured within the specified common mode range limits. 5. Guaranteed within the output limits of (V+ -0.3 V) to (V- +0.3 V). Tested with proprietary production test method. 6. PWDN input has an internal pullup resistor to V+ of approximately 800 k and is the major source of current consumption when PWDN is active (low). 7. The device has a controlled start-up behavior due to its complex open loop gain characteristics. Startup time applies to when supply voltage is applied or when PDWN is released.
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Storage Temperature Range [(V+) - (V-)] V- -0.3 -65 Min T yp Max 6.8 V+ +0.3 +150 Unit V V C
2. TYPICAL PERFORMANCE PLOTS
100
nV/Hz
1k 1000
100 100 nV/ Hz
10 10
10
1 0.001
0.010
0.1 Frequency (Hz)
1
10
11
10
10
100
100
1000
1k
10000 100000 100000 1E+07 Frequency 0 Freq u en c y
10k
100k
1M
10M
Figure 1. Noise vs. Frequency (Measured)
Figure 2. Noise vs. Frequency
200 150 100 50 0 -50 -100 -150 -200
100 75 50 25 nV 0 -25 -50 -75 -100 TIME(1HR)
= 13 nV
nV
0
1
2
3
4 6 5 TIME (Sec) TIME (Sec)
7
8
9
10
Figure 3. 0.01 Hz to 10 Hz Noise
Figure 4. Offset Voltage Stability (DC to 3.2 Hz)
Supply Current (mA)
2.0
1.9 Supply Current (mA)
1.5 1.0 0.5 0.0 -40 -20 0 20 40
6.7 V 5V 2.7 V
1.7 1.5 1.3 1.1 0.9 0.7 0.5 -40 -20 0 20 40
6.7 V 2.7 V
60
80
60
80
Temperature (C)
Temperature (C)
Figure 5. Supply Current vs. Temperature, CS3011
Figure 6. Supply Current vs. Temperature, CS3012
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Typical Performance Plots (Cont.)
1
1.5 Supply Current (mA) 1.4 1.3 1.2 1.1 1
2 3 4 5 6 7
Supply Current (mA)
0.9 0.8 0.7 0.6 0.5 Supply Voltage (V)
2
3
4
5
6
7
Supply Voltage (V)
Figure 7. Supply Current vs. Voltage, CS3011
Figure 8. Supply Current vs. Voltage, CS3012
500 400 300 200 100 0 -100 -200 -300 -400 -500
Gain (dB) Phase (Degrees)
GAIN
PHASE
1 1
10 10
100 100
10k 100k 1M 10M 10000 100000 100000 1E+07 0 Frequency (Hz) 100 Frequency (Hz) K
1k 1000
Figure 9. Open Loop Gain and Phase vs Frequency
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Typical Performance Plots (Cont.)
80
60 Gain (dB)
Phase (degrees)
40
20
0 0 -45 -90 -135 -180 -225 -270 -315 -360 10000 10 K 100000 100 K 1000000 1M 10000000 10 M
Frequency
Figure 10. Open Loop Gain and Phase vs Frequency (Expand-
CS3012 IB vs Common
200 Bias Current (pA) 150 100 50 0 -50 -100 -150 -200 0 1 2 3 4 5 Common Mode Voltage (Vs = 5V)
Figure 11. Input Bias Current vs Common Mode Voltage (CS3012) ABB+ A+
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Typical Performance Plots (Cont.)
V+ -50 -100 -150
V+ -50
-40C +125C
-100 -150
-40C +125C
Output Voltage (mV)
-200 -250
Output Voltage (mV)
+25C
-200 -250
+25C
+250 +200 +150 +100 +50 V-
+125C
+250 +200 +150
+125C
+25C
-40C
+25C
-40C
+100 +50
0
1
Output Current (mA)
2
3
4
5
V-
0
1
Output Current (mA)
2
3
4
5
Figure 12. Voltage Swing vs. Output Current (2.7 V)
Figure 13. Voltage Swing vs. Output Current (5 V)
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3. CS3011/CS3012 OVERVIEW
The CS301 1/CS3012 amplifiers are de signed for precision measu rement o f sign als from DC to 1 kHz when opera ting from a supply voltage of +2.7 V to +6.7 V ( 1.35 to 3.35 V). The amplifiers are designed with a patented architecture that utilizes multiple amplifier stages to yield very high open loop gain at frequencies of 1 kHz and below. The amplifiers yield low noise and low offset dr ift while consuming relatively low supply current . An increase in noise floor above 1 kHz is the result of intermediate stages of the amplifier being operated at very low currents. The amplifiers are intende d for amplifying small signals with large gains in applications where the output of the amplifier can be band-limited to frequencies below 1 kHz.
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3.1
Figure 14 illustrates the open loop gain and phase response of t he CS3011/CS3012. The gain slope of the amplifier is about -100 dB/decade between 500 Hz and 30 kHz and transitions to -2 0 dB/de-
Open Loop Gain and Phase Response
cade between 30 kHz and its unity gain crossover frequency at about 2.4 MHz. Phase margin at unity gain is abou t 70 degrees; gain marg in is abo ut 20 dB.
80
60 Gain (dB)
Phase (degrees)
40
20
0 0
-45 -90 -135 -180 -225 -270 -315 -360 10000 10 K 100000 100 K 1000000 1M 10000000 10 M
Figure 14. CS3011/CS3012 Open Loop Gain and Phase Response
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3.2 3.2.1 Open Loop Gain and Stability Compensation Discussion
al pole in the loop gain transfer function at a frequency of f = 1/(2R*Cin) where R is t he para llel combination of R1 and R2 (R1 || R2). A higher value for R produces a pole at a lower freq uency, thus reducing the phase margin. R1 is recommended to be less than or equal to 100 ohms, which results in a pole at 30 MHz or higher. If a higher value of R1 is desired, a compensation capacitor (C2) should be added in parallel with R2. C2 should be chosen such that R2*C2 R1*Cin.
The CS3011 and CS3012 achieve ultra-high open loop gain. Figure 15 il lustrates the ampl ifier in a non-inverting gain configuration. Th e ope n lo op gain and phase plo ts indicate that the amplifier is stable for closed-loop gains less than 50 V/V. For a gain of 50, the phase margin is between 40 and 60 de pending upon the load ing conditions. As shown in Figure 16 on page 11, the op amp has an input ca pacitance at the + and - signal input s of typically 50 pF. This capacitance adds an additionRS V in
Vo
R2
R1
Figure 15. Non-Inverting Gain Configuration
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Vin C in 50 pF Vo 50 pF C in
R2
R1 C2
Choose C2 so that R2 * C2 R 1 * C in
?
Figure 16. Non-Inverting Gain Configuration with Compensation
The feedback capacitor C2 is required for closedloop gains greater than 50 V/V. Th capacitor introe
duces a pole and a zero in th e loop gain transfer function.
s - 1 + ---- z 1 T = ---------------------- A ol s 1 + ---- p
1
1 1 P 1 = ------------------------------------ -----------------------2 ( R 1 || R 2 )C 2 2 ( R 1 C 2 )
for
R2 R1
1 Z 1 = ----------------------------------2 ( A x R 1 )C 2
where
R2 A = ----R1
1 Z 1 = -----------------------2 ( R 2 )C 2
This indicates that the sep aration of the pole and the zero is governed by the clo sed loop gain. It is required that th e ze ro falls o n the steep slo pe (-100 dB/decade) of the loop ga in plot so that
there is some gain higher than 0 dB (typically 20 dB) at the ha nd-over frequency (the frequ ency at which the slope changes from - 100 dB/decade to -20 dB/decade).
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The loop gain plot shown in Figure 17 i llustrates the unity gain configuration, and indicates how this is mo dified when using the amplifier in a hig her gain configuration with compensation. If it is configured for higher gain, for example, 60 dB, the x- axis will move up by 60 dB (line B). Capacitor C2 adds a zero and a pole. The modified plot indicates the effects of introducing the pole and zero due to capacitor C2 . The pole can be located at any frequency higher than the hand-over frequency, the zero has to be at a frequency lower than the handover freque ncy so as to provide ade quate ga in margin. The separation between the pole and the zero is governed by the closed loop gain. The zero (z1) occurs at the intersection o f the -100 dB/decade and -80 dB/decade slopes. The point X in the figure should be at closed loop gain plus 20 dB gain margin. The value for C2 = 1/(2R1p1). Using p1 = 500 kHz works very well and is independent of ga in. As the closed loop ga in is change d, the zero location is also modified if R1 remains fixed. Cap acitor C2 ca n be incre ased in value to limit the amplifier's rising noise above 1 kHz.
-100 dB/dec
|T| (Log gain)
z1 p1
-80 dB/dec
X
Margin B
-20 dB/dec
Desired Closed Loop Gain
50kHz 25 kHz 500 kHz 1MHz 2.4 MHz 5MHz
FREQUENCY
Figure 17. Loop Gain Plot: Unity Gain and with Pole-Zero Compensation
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3.2.2 Gain Calculations Summary and Recommendations Verify the Opamp Compensation:
Verify the opamp co mpensation using the ope nloop gain and pha se resp onse Bode plot in Figure 14. Plot the calculated clo sed loop gain transfer function and verify the following design criteria are met: * Pole P1 > opamp in ternal 50 kHz c rossover frequency * * P1 = 1 / [2 (R1| |R2) * C2], where P1 = 1 MHz To sim plify the ca lculation, set t he p ole t o P1 = 1 MHz. Z1 = 1 / (2 R2 * C2)
Condition #1: |Av| 50 and R1 100
The Opamp is inheren tly stable for |Av| 50 an d R1 100 . No C2 co mpensation cap acitor across R2 is required. * * |Av| = 1 config uration ha s 7 0 pha se margin and 20 dB gain margin. |Av| = 50 configuration ha s p hase ma rgin between 40 for C LOAD 100 pF and 60 for CLOAD = 0 pF.
Z1 < opamp internal 50 kHz crossover frequency Gain margin above the open-loop gain transfer function is re quired. A g ain margin of +2 0 dB above t he op en loop g ain transfer fun ction is optimal.
Condition #2: |Av| 50 and R1 > 100
Compensation capacitor C2 across R2 is required. Calculate C2 using the following formula: * C2 (R1 * Cin) / R2, where Cin = 50 pF
Condition #3: |Av| > 50
Compensation capacitor C2 across R2 is required. Calculate and verify a value for C2 using the following steps.
Calculate the Compensation Capacitor Value:
1) Calculate a value for C2 using the following formula: C2 = 1 / [2 (R1| |R2) * P1], where P1 = 1 MHz To simplify the calculation, set the pole of the filter to P1 = 1 MHz. P1 must be set h igher than the opamp's internal 50 kHz crossover frequency. 2) Calculate a second value for C2 using the following formula: C2 (R1 * Cin) / R2, where Cin = 50 pF 3) Use the la rger of t he two va lues calculated in steps 1 & 2.
3.3
The CS3011 single amplifier provides a powerdown function on pin 1. If this pin is left ope n the amplifier will operate normally. If the powerdown is asserted low, the amplifier enters a powered down state. Th ere is a pu ll-up resistor (approximately 800 k ohm) inside the amplifier from pin 1 to the V+ supply. The current through this pull-up resistor is the main source of current drain in the powerdown state.
Powerdown (PDWN)
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3.4
The CS3011 and CS3012 amplifiers are optimum for applications that require high gain and low drift. Figure 18 illustrates a thermopile amp lifier with a gain of 650 V/V. The thermopile outputs only a few millivolts when subjected to infrared radiation. The amplifier is compensated and bandlimited by C1 in combination with R2.
Applications
Figure 19 on page 14 illustrates a load cell bridg e amplifier with a gain of 768 V/V. The load cell is excited with +5 V and has a 1 mV/V sensitivity. Its full scale output signal is am plified to produce a f ully differential 3.8 V into the CS5510/ 2 A/D convert1 er. This circuit operates from +5 V.
CS3011
Dexter Research Thermopile ST60
R2 64.9k
R1 100
C1 0.015F
Figure 18. Thermopile Amplifier with a Gain of 650 V/V
+5 V VA
+5 V 0 .1 F VREF 100 A IN + 1 4 0 k 0 .2 2 F V+ CS SDO SCLK C S 5 5 1 0 /1 2
+5 V
+
x768
1 m V /V -
350
+ 365 0 .0 4 7 F
+
1 4 0 k
0 .2 2 F A IN 1 100 V-
C o u n te r /T im e r
S C L K = 1 0 k H) z t o 1 0 0 k H z (3 2 .7 6 8 n o m in a l)
S C L K = 1 0 k H z to 1 0 0 ( 3 2 .7 6 8
Figure 19. Load Cell Bridge Amplifier and A/D Converter
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4. ORDERING INFORMATION
Model Temperature Package
CS3011-ISZ CS3012-ISZ
-40 to +85 C
8-pin SOIC, Lead Free
5. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number Peak Reflow Temp 260 C MSL Rating* 2 Max Floor Life 365 Days
CS3011-ISZ CS3012-ISZ
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
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6. PACKAGE DRAWING 8L SOIC (150 MIL BODY) PACKAGE DRAWING
E
H
1 b D SEATING PLANE e A1 A L c
DIM A 0.0 A1 B C D E e H L
MIN 53 0.004 0.013 0.007 0.189 0.150 0.040 0.228 0.016 0
INCHES
MAX 0.069 0.010 0.020 0.010 0.197 0.157 0.060 0.244 0.050 8
MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.02 1.52 5.80 6.20 0.40 1.27 0 8
JEDEC # : MS-012
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7. REVISION HISTORY
Revision F2 F3 F4 F5 F6 Date SEP 2004 AUG 2005 AUG 2006 NOV 2007 JUL 2009 Changes Added lead-free device ordering information. Added MSL specifications. Updated legal notice. Added leaded (Pb) devices. Updated Typical Performance Plots. Removed Powerdown feature. Added additional information regarding open-loop and gain stability compensation. Removed lead-containing SOICs from ordering information.
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Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRR US PRODUCT THAT IS USED IN SUCH A MANNER. IF TH E CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS TH USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY E INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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